In general, a flash memory cell includes a gate in which a tunnel dielectric layer, a floating gate, a dielectric layer, and a control gate are laminated over a semiconductor substrate, and a junction region is formed over the semiconductor substrate on both sides of the gate. As hot electrons are injected into the floating gate, data is programmed into the flash memory cell, and, as injected electrons are discharged by F-N tunneling, data programmed into the flash memory cell is erased.
FIG. 1 is a sectional view illustrating a conventional method of forming a gate pattern of a flash memory device.
Referring to FIG. 1, a tunnel dielectric layer 11, a conductive layer 12 for a floating gate, a dielectric layer 13, a conductive layer 14 for a control gate, a metal electrode layer 15, and hard mask films 16, 17 are sequentially laminated over a semiconductor substrate 10. A patterning process is then performed to form a gate pattern.
In recent years, as semiconductor devices are becoming more highly integrated, the size of the pattern is decreased. Lateral damage at the time of an etch process of a gate pattern causes a bowing profile to occur. In particular, damage to the sidewalls of the metal electrode layer 15, occurring at the time of an etch process of the dielectric layer, results in increased resistance of word lines. Accordingly, the operation of a device becomes slow and electrical properties are degraded.